Display device, semiconductor device, and driving method thereof

ABSTRACT

An object is to provide a semiconductor device with improved operation. The semiconductor device includes a first transistor, and a second transistor electrically connected to a gate of the first transistor. A first terminal of the first transistor is electrically connected to a first line. A second terminal of the first transistor is electrically connected to a second line. The gate of the first transistor is electrically connected to a first terminal or a second terminal of the second transistor.

CROSS-REFERENCE TO RELATED APPLICATIONS

This application is a continuation of U.S. application Ser. No.17/087,801, filed Nov. 3, 2020, now allowed, which is a continuation ofU.S. application Ser. No. 16/809,663, filed Mar. 5, 2020, now U.S. Pat.No. 11,222,906, which is a continuation of U.S. application Ser. No.15/680,348, filed Aug. 18, 2017, now abandoned, which is a continuationof U.S. application Ser. No. 14/885,353, filed Oct. 16, 2015, nowabandoned, which is a divisional of U.S. application Ser. No.14/085,864, filed Nov. 21, 2013, now abandoned, which is a continuationof U.S. application Ser. No. 13/025,479, filed Feb. 11, 2011, now U.S.Pat. No. 8,599,998, which claims the benefit of a foreign priorityapplication filed in Japan as Serial No. 2010-036902 on Feb. 23, 2010,all of which are incorporated by reference.

TECHNICAL FIELD

One embodiment of the present invention relates to display devices. Forexample, one embodiment of the present invention relates to liquidcrystal display devices. One of the technical fields relates to adisplay device in which an image is displayed when a pixel is selectedby a gate signal line and a source signal line. Further, one of thetechnical fields relates to an electronic appliance with a displaydevice and a semiconductor device such as a driver circuit used in adisplay device.

BACKGROUND ART

Gate driver circuits including amorphous silicon transistors (alsoreferred to as a-Si TFTs) have been developed (see Patent Documents 1and 2, for example). Such a gate driver includes a transistor forcontrolling the timing of outputting a high voltage to a gate line (sucha transistor is also referred to as a pull up transistor). The pull uptransistor has a source and a drain one of which is connected to a clockline and the other of which is connected to a gate line. In addition,such a gate driver employs a driving method in which the potential of agate of the pull up transistor is made higher than the high (H-level)potential of a clock signal by capacitive coupling. In order to achievethis driving method, it is necessary to make the gate of the pull uptransistor be floating. It is therefore necessary to turn off all thetransistors that are connected to the gate of the pull up transistor.

REFERENCE

[Reference 1] Japanese Published Patent Application No. 2007-207413

[Reference 2] Japanese Published Patent Application No. 2008-009393

DISCLOSURE OF INVENTION

In conventional techniques, however, even when all the transistors thatare connected to a gate of a pull up transistor are turned off,electrical charge stored in the gate of the pull up transistor is lostas time passes because of the off-state current of the transistor. It istherefore difficult to lower the drive frequency of a semiconductordevice such as a gate driver circuit. Further, the range of the drivefrequency at which the semiconductor device can operate is narrow.Consequently, there is a limit to improvement in the drive capability ofthe semiconductor device.

In view of the problems, an object of one embodiment of the presentinvention is to improve operation of a semiconductor device including atransistor (a pull-up transistor) that controls the timing of when apredetermined voltage is outputted to a circuit located at thesubsequent stage. An object of one embodiment of the present inventionis to improve the drive capability of a semiconductor device including atransistor (a pull-up transistor) that controls the timing of when apredetermined voltage is outputted to a circuit located at thesubsequent stage.

One embodiment of the present invention is a semiconductor deviceincluding a first transistor, and a second transistor electricallyconnected to a gate of the first transistor. A first terminal of thefirst transistor is electrically connected to a first line. A secondterminal of the first transistor is electrically connected to a secondline. The gate of the first transistor is electrically connected to afirst terminal or a second terminal of the second transistor. In thesemiconductor device, the first transistor and the second transistor canhave an oxide semiconductor at least in their channel regions and have alow off-state current. Alternatively, at least the second transistor canhave an oxide semiconductor at least in its channel region and have alow off-state current. Specifically, the first transistor or the secondtransistor can have an off-state current of 1 aA/μm or less per 1 μm ofchannel width at room temperature (20° C. in this case). One or more ofthe second transistors can be provided in the semiconductor device. Itis preferable that when a plurality of the second transistors isprovided, all these transistors have an oxide semiconductor at least intheir channel regions and have a low off-state current. In thesemiconductor device, the second line can be electrically connected to acircuit located at the subsequent stage. Thus, the first transistor canserve as a transistor (a pull-up transistor) that controls the timing ofwhen a predetermined voltage is outputted to the circuit located at thesubsequent stage.

One embodiment of the present invention is a semiconductor deviceincluding a first transistor; a second transistor; and a thirdtransistor. A first terminal of the first transistor is electricallyconnected to a first line, and a second terminal of the first transistoris electrically connected to a second line. A first terminal of thesecond transistor is electrically connected to the second line; a secondterminal of the second transistor is electrically connected to a gate ofthe first transistor; and a gate of the second transistor iselectrically connected to the first line. A first terminal of the thirdtransistor is electrically connected to a third line; a second terminalof the third transistor is electrically connected to the gate of thefirst transistor; and a gate of the third transistor is electricallyconnected to the third line. At least a channel region of the first tothird transistors can be formed using an oxide semiconductor. Off-statecurrent of the first to third transistors can be 1 aA/μm or less.Alternatively, at least a channel region of at least the second andthird transistors can be formed using an oxide semiconductor. Off-statecurrent of at least the second and third transistors can be 1 aA/μm orless.

One embodiment of the present invention is a semiconductor deviceincluding a first transistor; a second transistor; and a thirdtransistor. A first terminal of the first transistor is electricallyconnected to a first line, and a second terminal of the first transistoris electrically connected to a second line. A first terminal of thesecond transistor is electrically connected to a third line; a secondterminal of the second transistor is electrically connected to a fourthline. A first terminal of the third transistor is electrically connectedto the third line; a second terminal of the third transistor iselectrically connected to the gate of the first transistor; and a gateof the third transistor is electrically connected to the fourth line. Atleast a channel region of the first to third transistors can be formedusing an oxide semiconductor. Off-state current of the first to thirdtransistors can be 1 aA/μm or less. Alternatively, at least a channelregion of at least the third transistor can be formed using an oxidesemiconductor. Off-state current of at least the third transistor can be1 aA/μm or less.

One embodiment of the present invention is a semiconductor deviceincluding a first transistor; a second transistor; a third transistor;and a fourth transistor. A first terminal of the first transistor iselectrically connected to a first line, and a second terminal of thefirst transistor is electrically connected to a second line. A firstterminal of the second transistor is electrically connected to a thirdline; a second terminal of the second transistor is electricallyconnected to a gate of the first transistor; and a gate of the secondtransistor is electrically connected to the first line. A first terminalof the third transistor is electrically connected to the third line; asecond terminal of the third transistor is electrically connected to thegate of the first transistor; and a gate of the third transistor iselectrically connected to the gate of the second transistor. A firstterminal of the fourth transistor is electrically connected to a fourthline; a second terminal of the fourth transistor is electricallyconnected to the gate of the first transistor; and a gate of the fourthtransistor is electrically connected to the fourth line. At least achannel region of the first to fourth transistors can be formed using anoxide semiconductor. Off-state current of the first to fourthtransistors can be 1 aA/μm or less. Alternatively, at least a channelregion of at least the second to fourth transistors can be formed usingan oxide semiconductor. Off-state current of at least the second tofourth transistors can be 1 aA/μm or less.

One embodiment of the present invention is a semiconductor deviceincluding a first transistor; a second transistor; a third transistor;and a fourth transistor. A first terminal of the first transistor iselectrically connected to a first line, and a second terminal of thefirst transistor is electrically connected to a second line. A firstterminal of the second transistor is electrically connected to a thirdline; a second terminal of the second transistor is electricallyconnected to a gate of the first transistor; and a gate of the secondtransistor is electrically connected to the first line. A first terminalof the third transistor is electrically connected to a fourth line; asecond terminal of the third transistor is electrically connected to thegate of the first transistor; and a gate of the third transistor iselectrically connected to the fourth line. A first terminal of thefourth transistor is electrically connected to the third line; a secondterminal of the fourth transistor is electrically connected to the gateof the first transistor; and a gate of the fourth transistor iselectrically connected to a fifth line. At least a channel region of thefirst to fourth transistors can be formed using an oxide semiconductor.Off-state current of the first to fourth transistors can be 1 aA/μm orless. Alternatively, at least a channel region of at least the second tofourth transistors can be formed using an oxide semiconductor. Off-statecurrent of at least the second to fourth transistors can be 1 aA/μm orless.

Another embodiment of the present invention is a display deviceincluding a gate driver circuit and using the above semiconductor deviceas the gate driver circuit.

In this specification, the explicit description “X and Y are connectedto each other” may mean that X and Y are electrically connected to eachother. Here, X and Y each denote an object (e.g., a device, an element,a circuit, a line, an electrode, a terminal, a conductive film, a layer,or the like). An example of the case where X and Y are electricallyconnected to each other is a case where one or more elements that enableelectrical connection between X and Y (e.g., a switch, a transistor, acapacitor, an inductor, a resistor, and a diode) are connected between Xand Y.

One embodiment of the present invention is a semiconductor deviceincluding a transistor (a pull-up transistor) that controls the timingof when a high voltage is outputted to a circuit located at thesubsequent stage. In this semiconductor device, charge stored in a gateof the pull-up transistor is held for a long period of time. Therefore,it is possible to reduce the drive frequency of the semiconductor deviceand to widen the range of the drive frequency at which the semiconductordevice can operate. Thus, the operation of the semiconductor device canbe improved. Alternatively, the drive capability of the semiconductordevice can be improved.

BRIEF DESCRIPTION OF DRAWINGS

In the accompanying drawings:

FIGS. 1A to 1F are diagrams showing configurations of circuits ofEmbodiment 1;

FIG. 2A is a timing diagram for describing the operation of the circuitof Embodiment 1, and FIGS. 2B to 2E are schematic views for describingthe operation of the circuit of Embodiment 1;

FIGS. 3A to 3C are schematic views for describing the operation of thecircuit of Embodiment 1;

FIGS. 4A to 4F are diagrams showing configurations of circuits ofEmbodiment 1;

FIGS. 5A and 5B are timing diagrams for describing the operation of thecircuit of Embodiment 1;

FIGS. 6A to 6F are diagrams showing configurations of circuits ofEmbodiment 1;

FIG. 7A is a diagram showing a configuration of a circuit of Embodiment1, and FIGS. 7B to 7F are schematic views for describing the operationof the circuit of Embodiment 1;

FIG. 8 is a diagram showing a configuration of a shift register circuitof Embodiment 2;

FIG. 9 is a timing diagram for describing the operation of the shiftregister circuit of Embodiment 2;

FIG. 10 is a diagram showing a configuration of a shift register circuitof Embodiment 2;

FIGS. 11A to 11D are examples of diagrams for describing steps offabricating a transistor of Embodiment 3;

FIGS. 12A to 12C are diagrams showing structures of display devices ofEmbodiment 4;

FIGS. 13A to 13H are diagrams showing devices embodying the technicalidea of the present invention; and

FIGS. 14A to 14H are diagrams showing devices embodying the technicalidea of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiments will be described below with reference to the drawings. Notethat the embodiments can be implemented in various different ways. Itwill be readily appreciated by those skilled in the art that modes anddetails of the embodiments can be changed in various ways withoutdeparting from the spirit and scope of the present invention. Therefore,the present invention should not be construed as being limited to thedescription of the embodiments. Note that in structures described below,the same portions or portions having similar functions are denoted bycommon reference numerals in different drawings, and detaileddescription thereof is not repeated. In the reference drawings, thesize, the thickness of layers, or regions is exaggerated for clarity insome cases. Therefore, the embodiments of the present invention are notlimited to such scales.

Embodiment 1

In this embodiment, a circuit in a display device that is one embodimentof the present invention will be described.

FIG. 1A shows an example of the configuration of a circuit including atransistor 101, a transistor 102, a transistor 103, a transistor 104, atransistor 105, and a circuit 200. The transistors included in thecircuit shown in FIG. 1A are n-channel transistors. An n-channeltransistor is turned on when a potential difference between a gate and asource is higher than the threshold voltage.

Note that the transistors included in the circuit shown in FIG. 1A caneach have a semiconductor layer of an oxide semiconductor that isintrinsic (i-type) or substantially intrinsic, has an adequately loweredhydrogen concentration which makes the oxide semiconductor highlypurified, and has an adequately low carrier concentration. This leads toimprovement in the subthreshold swing of the transistor, a reduction inthe off-state current of the transistor, improvement in the withstandvoltage of the transistor, and improvement in the temperaturecharacteristics of the transistor.

It is acceptable that one or some transistors have semiconductor layersof the oxide semiconductor, and the other transistors have semiconductorlayers of a semiconductor different from the oxide semiconductor (forexample, silicon (e.g., amorphous silicon, microcrystalline silicon, orpolycrystalline silicon), an organic semiconductor, or the like). Notethat at least a transistor to which a source or a drain of thetransistor 101 is electrically connected has a semiconductor layer ofthe oxide semiconductor.

Next, connections in the circuit shown in FIG. 1A will be described. Afirst terminal (one of a source and a drain) of the transistor 101 isconnected to a line 111, and a second terminal (the other of the sourceand the drain) of the transistor 101 is connected to a line 112. A firstterminal of the transistor 102 is connected to a line 113; a secondterminal of the transistor 102 is connected to the line 112; and a gateof the transistor 102 is connected to the circuit 200. A first terminalof the transistor 103 is connected to the line 112; a second terminal ofthe transistor 103 is connected to the gate of the transistor 101; and agate of the transistor 103 is connected to the line 111. A firstterminal of the transistor 104 is connected to a line 114; a secondterminal of the transistor 104 is connected to the gate of thetransistor 101; and a gate of the transistor 104 is connected to theline 114. A first terminal of the transistor 105 is connected to theline 113; a second terminal of the transistor 105 is connected to thegate of the transistor 101; and a gate of the transistor 105 isconnected to a line 115. Note that a node 11 represents a connectionpoint of the gate of the transistor 101; the second terminal of thetransistor 103; the second terminal of the transistor 104; and thesecond terminal of the transistor 105. A node 12 represents a connectionpoint of the gate of the transistor 102 and the circuit 200.

Note that the configuration of a circuit relating to a display devicethat is one embodiment of the present invention is not limited to theconfiguration of the circuit shown in FIG. 1A. For example, as shown inFIG. 1B, the gate of the transistor 103 can be connected to the gate ofthe transistor 102. As another example, as shown in FIG. 1C, the firstterminal of the transistor 103 can be connected to the line 113 and thegate of the transistor 103 can be connected to the gate of thetransistor 102. As another example, as shown in FIG. 1D, the secondterminal of the transistor 105 can be connected to the line 112. Asanother example, as shown in FIG. 1E, the first terminal of thetransistor 104 can be connected to a line 116. As another example, asshown in FIG. 1F, the gate of the transistor 104 can be connected to theline 116. Note that at least two or more of the configurations shown inFIG. 1B to 1F can be combined with each other. For example, when theconfiguration shown in FIG. 1C and the configuration shown in FIG. 1Eare combined with each other, the first terminal of the transistor 103can be connected to the line 113 and the first terminal of thetransistor 104 can be connected to the line 116.

Note that the circuit 200 can be connected to a predetermined line ornode depending on its structure. For example, the circuit 200 can beconnected to at least one of the line 111, the line 112, the line 113,the line 114, and the node 11.

A clock signal is inputted to the line 111. An output signal of thecircuit of this embodiment is inputted to the line 112. Potential V2 isapplied to the line 113. A start pulse is inputted to the line 114. Areset signal is inputted to the line 115. Here, the potential of theH-level signal inputted to the line 111, the line 112, the line 114, andthe line 115 is referred to as potential V1 for convenience, while thepotential of the L-level signal inputted to the line 111, the line 112,the line 114, and the line 115 is referred to as the potential V2 forconvenience.

The line 111 is used for transmitting a signal such as a clock signalfrom an external circuit such as a controller to the circuit of thisembodiment. The line 111 functions as a signal line or a clock line. Theline 112 is used for transmitting an output signal of the circuit ofthis embodiment to a circuit such as a pixel circuit or a demultiplexer.The line 112 functions as a signal line or a gate line. The line 113 isused for supplying a power supply voltage such as the potential V2 froman external circuit such as a power supply circuit to the circuit ofthis embodiment. The line 113 functions as a power supply line, anegative supply line, or a ground line. The line 114 is used fortransmitting a start signal from another circuit or an external circuitsuch as a timing controller to the circuit of this embodiment. The line114 functions as a signal line. The line 115 is used for transmitting areset signal from another circuit or an external circuit such as atiming controller to the circuit of this embodiment. The line 115functions as a signal line.

The transistor 101 functions as a switch for controlling continuitybetween the line 111 and the line 112. Further, the transistor 101 has afunction of controlling the timing of raising the potential of the node11 by capacitive coupling between the second terminal and the gate ofthe transistor 101. The transistor 102 functions as a switch forcontrolling continuity between the line 113 and the line 112. Thetransistor 103 functions as a switch for controlling continuity betweenthe line 112 and the node 11. The transistor 104 functions as a switchfor controlling continuity between the line 114 and the node 11.Further, the transistor 104 functions as a diode whose input terminal isconnected to the line 114 and whose output terminal is connected to thenode 11. The transistor 105 functions as a switch for controllingcontinuity between the line 113 and the node 11.

Next, an example of the operation of the circuits in FIGS. 1A to 1F willbe described with reference to a timing diagram of FIG. 2A and schematicdiagrams of FIGS. 2B to 2E and FIGS. 3A to 3C. Here, the circuit in FIG.1A will be described as an example.

FIG. 2A is an example of a timing diagram showing the potential of theline 111, the line 114, the line 115, the line 112, the node 11, and thenode 12. The timing diagram of FIG. 2A includes a period A, a period B,a period C, a period D, and a period E. The timing diagram of FIG. 2Aincludes a period in which the period A, the period B, and the period Cappear in order; and a period in which the period D and the period Eappear alternately.

First, the period A will be described with reference to FIGS. 2A to 2C.In the period A, the potential of the line 111 (referred to as potentialV111) becomes V2 (low potential). Consequently, the transistor 103 isturned off, so that continuity between the line 112 and the node 11 isbroken. The potential of the line 114 (referred to as potential V114)becomes V1 (high potential). Consequently, the transistor 104 is turnedon, so that continuity between the line 114 and the node 11 isestablished. The potential of the line 115 (referred to as potentialV115) becomes V2. Consequently, the transistor 105 is turned off, sothat continuity between the line 113 and the node 11 is broken. Thus,the potential of the line 114 is applied to the node 11, so that thepotential of the node 11 (referred to as potential V11) starts toincrease. Then, the potential of the node 11 exceeds V2+Vth101 (Vth101is the threshold voltage of the transistor 101). The transistor 101 istherefore turned on, so that continuity between the line 112 and theline 111 is established. The potential of the node 12 (referred to aspotential V12) becomes V2 or at least less than V2+Vth102 (Vth102 is thethreshold voltage of the transistor 102) because of the circuit 200.Thus, the transistor 102 is turned off, so that continuity between theline 113 and the line 112 is broken. Consequently, the potential of theline 111 is applied to the line 112, so that the potential of the line112 (referred to as potential V112) becomes V2 (see FIG. 2B).

After that, the potential of the node 11 further increases. Then, thepotential of the node 11 increases to V1−Vth104 (Vth104 is the thresholdvoltage of the transistor 104). Thus, the transistor 104 is turned off,so that continuity between the line 114 and the node 11 is broken. Thenode 11 becomes therefore floating, so that the potential of the node 11is maintained at V1−Vth104 (see FIG. 2C).

The period B will be described with reference to FIGS. 2A and 2D. In theperiod B, the potential of the node 12 remains to be V2 or less thanV2+Vth102 because of the circuit 200. Consequently, the transistor 102remains off, so that continuity between the line 113 and the line 112remains broken. The potential of the line 111 becomes V1. Thus, thetransistor 101 remains on, and the potential of the line 112 increases.The transistor 103 is turned on at the same time, so that continuitybetween the line 112 and the node 11 is established. Note that thetransistor 103 is turned off when the potential of the line 112 reachesV1−Vth103 (Vth103 is the threshold voltage of the transistor 103).Continuity between the line 112 and the node 11 is therefore broken. Thepotential of the line 114 becomes V2. Consequently, the transistor 104remains off, so that continuity between the line 114 and the node 11remains broken. The potential of the line 115 remains to be V2. Thus,the transistor 105 remains off, so that continuity between the line 113and the node 11 remains broken. The node 11 becomes therefore floating.The potential of the line 112 keeps increasing here. Consequently, thepotential of the node 11 can increase to V1+Vth101+Va (Va is a positivenumber) because of parasitic capacitance between the gate and the secondterminal of the transistor 101. This is so-called bootstrap operation.Thus, the potential of the line 112 can increase to the potential V1(see FIG. 2D).

The period C will be described with reference to FIGS. 2A and 2E andFIG. 3A. In the period C, the potential of the line 111 becomes V2.Consequently, the transistor 103 remains off, so that continuity betweenthe line 112 and the node 11 remains broken. The potential of the line114 remains to be V2. Thus, the transistor 104 remains off, so thatcontinuity between the line 114 and the node 11 remains established. Thepotential of the line 115 becomes V1. Consequently, the transistor 105is turned on, so that continuity between the line 113 and the node 11 isestablished. The potential of the line 113 is therefore applied to thenode 11. Since the potential of the line 113 is V2, the potential of thenode 11 becomes V2. Thus, the transistor 101 is turned off, so thatcontinuity between the line 111 and the line 112 is broken. Thepotential of the node 12 remains less than V2+Vth102 because of thecircuit 200. Consequently, the transistor 102 remains off, so thatcontinuity between the line 113 and the line 112 remains broken (seeFIG. 2E). Note that in many cases, the timing of when the potential ofthe line 111 becomes V2 comes earlier than the timing of when thetransistor 101 is turned off. For this reason, the potential of the line111 is applied to the line 112 before the transistor 101 is turned off,so that the potential of the line 112 becomes V2 (see FIG. 3A).

The period D will be described with reference to FIG. 2A and FIG. 3B. Inthe period D, the potential of the line 111 becomes V1. Consequently,the transistor 103 is turned on, so that continuity between the line 112and the node 11 is established. The potential of the line 114 remains tobe V2. Thus, the transistor 104 remains off, so that continuity betweenthe line 114 and the node 11 remains broken. The potential of the line115 becomes V2. Consequently, continuity between the line 113 and thenode 11 is broken. The potential of the node 12 exceeds V2+Vth102because of the circuit 200. Thus, the transistor 102 is turned on, sothat continuity between the line 113 and the line 112 is established.The potential of the line 113 is therefore applied to the node 11, sothat the potential of the node 11 becomes V2. Thus, the transistor 101is turned off, so that continuity between the line 111 and the line 112is broken. The potential of the line 113 is applied to the line 112, sothat the potential of the line 112 becomes V2 (see FIG. 3B).

The period E will be described with reference to FIG. 2A and FIG. 3C. Inthe period E, the potential of the line 111 becomes V2. Consequently,the transistor 103 is turned off, so that continuity between the line112 and the node 11 is broken. The potential of the line 114 remains tobe V2. Thus, the transistor 104 remains off, so that continuity betweenthe line 114 and the node 11 remains broken. The potential of the line115 remains to be V2. Consequently, continuity between the line 113 andthe node 11 is broken. The potential of the node 12 becomes V2 or lessthan V2+Vth102 because of the circuit 200. Thus, the transistor 102 isturned off, so that continuity between the line 113 and the line 112 isbroken. The node 11 becomes therefore floating, so that the potential ofthe node 11 remains to be V2. Thus, the transistor 101 remains off, sothat continuity between the line 111 and the line 112 remains broken.The line 112 becomes floating, so that the potential of the line 112remains to be V2 (see FIG. 3C).

Note that for the semiconductor device shown in FIG. 1C, in the periodD, the potential of the node 12 preferably exceeds V2+Vth102 and alsoV2+Vth103. In this case, the transistor 103 is turned on, so thatcontinuity between the line 113 and the node 11 is established.Consequently, the potential of the line 113 is applied to the node 11.Thus, the potential of the line 113 is applied to the node 11 through asingle transistor, so that the potential of the node 11 can bestabilized.

Note that for the circuit shown in FIG. 1D, in the period C, continuitybetween the line 113 and the line 112 is established when the transistor105 is turned on. Consequently, the potential of the line 113 is appliedto the line 112. Thus, the fall time of V112 can be shortened.

Note that for the circuit shown in FIG. 1E, the potential of the line116 is preferably V2 in the period A. In the periods B to E, thepotential of the line 116 can be either V1 or V2. The voltage V1 cantherefore be applied to the line 116. Alternatively, a clock signal thatis out of phase with the clock signal inputted to the line 111 can beinputted to the line 116. Alternatively, for example, a signal obtainedby inverting the clock signal inputted to the line 111 can be inputtedto the line 116. For the semiconductor device shown in FIG. 1F, thepotential of the line 116 preferably becomes V1 in the period A, and V2in the period B. In the periods C to E, the potential of the line 116can be either V1 or V2. A clock signal that is out of phase with theclock signal inputted to the line 111 can be inputted to the line 116.Alternatively, a signal obtained by inverting the clock signal inputtedto the line 111 can be inputted to the line 116.

As described above, in the above-described semiconductor devices, thepotential of the line 112 can be made equal to the potential of the line111 by using the bootstrap operation.

Note that in conventional techniques, the transistors have a highsubthreshold swing. This causes any of the following problems: the timefrom when the potential of the line 114 becomes V1 until when thetransistor 104 is turned off is long; it is difficult to increase drivefrequency because it is necessary to extend the period A; the rise timeof V112 is long (the rise time of the output signal is long); a loadthat can be applied to the line 112 is light; the channel width of thetransistor 101 is large; and the layout area is large.

In contrast, in this embodiment, the transistors have a low subthresholdswing. Drive capability can therefore be improved. For example, when thesubthreshold swing of the transistor 104 is low, it is possible toshorten the time from when the potential of the line 114 is V1 untilwhen the transistor 104 is turned on. Consequently, the length of theperiod A can be shortened, leading to improvement in drive frequency. Asanother example, when the subthreshold swing of the transistor 104 islow, it is possible to shorten the rise time of V112. Alternatively,even when a heavy load is applied to the line 112, the load can bedriven. Alternatively, the channel width of the transistor 101 can bereduced, leading to a reduction in layout area.

Note that in conventional techniques, the transistors have a highoff-state current. This causes any of the following problems: the amountof electrical charge lost from the node 11 as time passes is large; thepotential of the node 11 is decreased; the time during which thepotential of the node 11 can be kept higher than a value at which thetransistor 101 is turned on is short; it is difficult to lower drivefrequency; and the range of the drive frequency at which thesemiconductor device can operate is narrowed.

In contrast, in this embodiment, the transistors have a low off-statecurrent. Drive capability can therefore be improved. For example, whenthe off-state current of the transistor 103, the transistor 104, and thetransistor 105 is low, the amount of electrical charge lost from thenode 11 can be decreased. Consequently, a reduction in the potential ofthe node 11 can be suppressed. That is, the time during which thepotential of the node 11 can be kept higher than a value at which thetransistor 101 is turned on can be extended. As a result, the drivefrequency can be lowered; thus, the range of the drive frequency atwhich the semiconductor device can operate can be widened.

The circuits shown in FIGS. 1A to 1F can additionally include an elementsuch as a transistor. An example will be described.

FIG. 4A shows an example of the circuit shown in FIG. 1A including atransistor 121. The circuits shown in FIGS. 1B to 1F can include thetransistor 121 in the same way. A first terminal of the transistor 121is connected to the line 113. A second terminal of the transistor 121 isconnected to the line 112. A gate of the transistor 121 is connected tothe line 116. A clock signal is preferably inputted to the line 116.Thus, in the period E, the transistor 121 is turned on, so that thepotential of the line 113 is applied to the line 112. Consequently,noise in the line 112 can be reduced.

FIG. 4B shows an example of the circuit shown in FIG. 1A including atransistor 122. The circuits shown in FIGS. 1B to 1F and FIG. 4A caninclude the transistor 122 in the same way. A first terminal of thetransistor 122 is connected to the line 113. A second terminal of thetransistor 122 is connected to the line 112. A gate of the transistor122 is connected to the line 115. Thus, in the period C, the transistor122 is turned on, allowing the potential of the line 113 to be appliedto the line 112. Consequently, the rise time of V112 can be shortened.

FIG. 4C shows an example of the circuit shown in FIG. 1A including atransistor 123. The circuits shown in FIGS. 1B to 1F and FIGS. 4A and 4Bcan include the transistor 123 in the same way. A first terminal of thetransistor 123 is connected to the line 114. A second terminal of thetransistor 123 is connected to the node 11. A gate of the transistor 123is connected to the line 116. Thus, also in the period E, the potentialof the line 114 can be applied to the node 11. Consequently, noise inthe node 11 can be reduced.

FIG. 4D shows an example of the circuit shown in FIG. 1A including atransistor 124. The circuits shown in FIGS. 1B to 1F and FIGS. 4A to 4Ccan include the transistor 124 in the same way. A first terminal of thetransistor 124 is connected to the line 111. A second terminal of thetransistor 124 is connected to a line 117. A gate of the transistor 124is connected to the node 11. Thus, the potential of the line 117 can bechanged at the same timing as the potential of the line 112. In thiscase, one of the line 112 and the line 117 is connected to a load, andthe other is connected to another circuit. Hence, the other of thecircuit can be driven without being affected by the change in thepotential of the one of the line 112 and the line 117 due to the load.

FIG. 4E shows an example of the circuit shown in FIG. 1A including thetransistor 124 and a transistor 125. The circuits shown in FIGS. 1B to1F and FIGS. 4A to 4C can include the transistor 124 and the transistor125 in the same way. A first terminal of the transistor 125 is connectedto the line 113. A second terminal of the transistor 125 is connected tothe line 117. A gate of the transistor 125 is connected to the node 12.Thus, the potential of the line 117 can be kept to be V2. Alternatively,noise in the line 117 can be reduced.

FIG. 4F shows an example of the circuit shown in FIG. 1A including acapacitor 126. The circuits shown in FIGS. 1B to 1F and FIGS. 4A to 4Ecan include the capacitor 126 in the same way. The capacitor 126 isplaced between the gate and the second terminal of the transistor 101.

Note that the circuits shown in FIGS. 1B to 1F can each include two ormore elements selected from the capacitor 126 and the transistors 121 to125.

Not only the timing diagram of FIG. 2A but also various other timingdiagrams can be applied to the circuits of this embodiment. An examplewill be described. For example, the potential of the node 12 ispreferably less than V2+Vth102 at least in the period B of the periods Ato E. In this case, in the periods A, C, D, and E, the potential of thenode 12 can be less than V2+Vth102 or more than V2+Vth102. Note that inone of the period D and the period E (the period D in particular), thepotential of the node 12 is preferably a value exceeding V2+Vth102, andin the other of the period D and the period E (the period E inparticular), the potential of the node 12 is preferably less thanV2+Vth102. Hence, it is possible to shorten the time during which thetransistor 102 is on and thus to suppress shifts in the thresholdvoltage of the transistor 102. Note that for the circuit shown in FIG.1C, in the period A, the transistor 103 is turned on when the potentialof the node 12 exceeds V2+Vth102, causing a reduction in the potentialof the node 11. For this reason, in the period A, the potential of thenode 12 is preferably less than V2+Vth102. As another example, a signalinputted to the line 111 can be non-balanced, as shown in FIG. 5A. Thus,in the period C, the timing of when the potential of the line 115becomes V1 can be later than the timing of when the potential of theline 111 becomes V2. Consequently, the fall time of V112 can beshortened. As another example, a signal inputted to the line 111 can bea multiphase clock signal, as shown in FIG. 5B. Consequently, powerconsumption can be reduced. Note that FIG. 5B is an example of a timingdiagram obtained when a four-phase clock signal is inputted to the line111.

The W/L (W: channel width and L: channel length) ratio of the transistor101 is preferably higher than those of the transistor 103, thetransistor 104, the transistor 105, the transistor 121, the transistor122, the transistor 123, the transistor 124, and the transistor 125.Consequently, it is possible to shorten the rise time and the fall timeof V112. Specifically, the W/L ratio of the transistor 101 is preferablytwice or more and less than 20 times the W/L ratio of the transistor104, more preferably 3 times or more and less than 15 times the W/Lratio of the transistor 104, still more preferably 5 times or more andless than 12 times the W/L ratio of the transistor 104. As anotherexample, the W/L ratio of the transistor 105 is preferably lower thanthat of the transistor 104. Consequently, in the period C, it ispossible to delay the timing of when the transistor 101 is turned offand thus shorten the fall time of V112. Specifically, the W/L ratio ofthe transistor 105 is preferably 0.3 times or more and less than 1 timethe W/L ratio of the transistor 104, more preferably 0.4 to 0.9 timesthe W/L ratio of the transistor 104, still more preferably 0.5 to 0.8times the W/L ratio of the transistor 104. As another example, the W/Lratio of the transistor 103 is preferably lower than that of thetransistor 104. Consequently, it is possible to prevent the potential ofthe node 11 from decreasing too much in the period B. Specifically, theW/L ratio of the transistor 103 is preferably 0.1 times or more and lessthan 1 time the W/L ratio of the transistor 104, more preferably 0.3 to0.9 times the W/L ratio of the transistor 104, still more preferably 0.4to 0.7 times the W/L ratio of the transistor 104.

For example, the W/L ratio of the transistor 122 is preferably higherthan that of the transistor 102. Consequently, it is possible to shortenthe fall time of V112. Specifically, the W/L ratio of the transistor 122is preferably twice or more and less than 20 times the W/L ratio of thetransistor 102, more preferably 3 to 15 times the W/L ratio of thetransistor 102, still more preferably 5 times or more and less than 10times the W/L ratio of the transistor 102. As another example, the W/Lratio of the transistor 124 is preferably lower than that of thetransistor 101. This is because a load connected to the line 117 islighter than that connected to the line 112 in many cases. As anotherexample, the W/L ratio of the transistor 125 is preferably lower thanthat of the transistor 102. This is because a load connected to the line117 is lighter than that connected to the line 112 in many cases.

For example, the amplitude voltage of the node 12 is preferably lessthan the amplitude voltage of at least one of the node 11, the line 111,the line 112, the line 114, the line 115, the line 116, and the line117. Consequently, it is possible to reduce power consumption.Specifically, the amplitude voltage of the node 12 is preferably 0.3times or more and less than 1 time the amplitude voltage of the line111, more preferably 0.5 times or more and less than 1 time theamplitude voltage of the line 111, still more preferably 0.6 to 0.9times the amplitude voltage of the line 111. As another example, theamplitude voltage of the node 11 preferably exceeds the amplitudevoltage of at least one of the node 12, the line 111, the line 112, theline 114, the line 115, the line 116, and the line 117. Consequently, itis possible to increase a potential difference between the gate and thesource of the transistor 101 and thus to shorten the rise time and thefall time of V112. Specifically, the amplitude voltage of the node 11 ispreferably more than the amplitude voltage of the line 111 and twice orless the amplitude voltage of the line 111, more preferably 1.2 to 1.8times the amplitude voltage of the line 111, still more preferably 1.4to 1.6 times the amplitude voltage of the line 111.

For example, the time during which the transistor 102 is off ispreferably longer than the time during which V111 is high.

Note that in a technique using amorphous silicon, the mobility of atransistor is low. Further, it is necessary to increase the channelwidth of the transistor 101 in order that the transistor 101 may drive aheavy load (e.g., a gate line). Consequently, the channel width of thetransistor 101 is larger than the width of the line 111. In contrast,the mobility of the transistor used in the circuit of this embodiment ishigher than that of a transistor using amorphous silicon. Consequently,it is possible to reduce the channel width of the transistor 101.

For this reason, the channel width of the transistor 101 is preferablysmaller than at least one of the widths of the line 111. Specifically,the channel width of the transistor 101 is preferably 0.3 times or moreand less than 1 time the width of the line 111, more preferably 0.4 to0.9 times as large as the width of the line 111, still more preferably0.5 to 0.8 times as large as the width of the line 111.

Next, a specific example of the circuit 200 will be described. FIG. 7Ashows an example of the configuration of the circuit 200 including acapacitor 201 and a transistor 202. One electrode of the capacitor 201is connected to the line 111. The other electrode of the capacitor 201is connected to the node 12. A first terminal of the transistor 202 isconnected to the line 113. A second terminal of the transistor 202 isconnected to the node 12. A gate of the transistor 202 is connected tothe node 11. Note that the gate of the transistor 202 can be connectedto the line 112 or the line 114.

Next, an example of the operation of the circuit 200 will be describedwith reference to FIGS. 7B to 7F.

In the period A and the period B, the potential of the node 11 can be ahigh potential (e.g., a value exceeding V2+Vth202 (Vth202 is thethreshold voltage of the transistor 202)). For example, the value of thepotential of the node 11 is V1−Vth104 in the period A, and V1+Vth101+Vain the period B. Consequently, the transistor 202 is turned on, andcontinuity between the line 113 and the node 12 is established. Thepotential of the line 113 is therefore applied to the node 12. Since thepotential of the line 113 is V2, the potential of the node 12 becomes V2(see FIG. 7B).

In the period C, the potential of the line 111 becomes V2. Thetransistor 202 remains on here, so that continuity between the line 113and the node 12 remains established. Consequently, the potential of theline 113 is still applied to the node 12, so that the potential of thenode 12 remains to be V2. Here, a potential difference between the line111 and the node 12 is held in the capacitor 201. Then, the potential ofthe node 11 becomes V2. Consequently, the transistor 202 is turned off,and continuity between the line 113 and the node 12 is broken. The node12 becomes therefore floating. Note that the potential of the node 12 iskept to be V2 by the capacitor 201 (see FIG. 7C).

In the period D, the potential of the node 11 remains to be V2.Consequently, the transistor 202 remains off, so that continuity betweenthe line 113 and the node 12 remains broken. The potential of the line111 becomes V1 here. The potential of the node 12 is therefore increasedby capacitive coupling of the capacitor 201 (see FIG. 7D). In the periodE, the potential of the node 11 remains to be V2. Thus, the transistor202 remains off, so that continuity between the line 113 and the node 12remains broken. The potential of the line 111 becomes V2 here.Consequently, the potential of the node 12 is decreased by capacitivecoupling of the capacitor 201 (see FIG. 7E).

As described above, a circuit in which the potential of the node 12 canbe controlled can be formed with a few elements.

Note that as shown in FIG. 7F, it is possible to form a transistor 203in the circuit shown in FIG. 7A. A first terminal of the transistor 203is connected to the line 113. A second terminal of the transistor 203 isconnected to the node 12. A gate of the transistor 203 is connected tothe line 114. The transistor 203 is on in the period A, and is off inthe periods B to E. The potential of the line 113 is therefore appliedto the node 12 in the period A, allowing the fall time of V12 in theperiod A to be shortened. When the gate of the transistor 203 isconnected to the line 115, the transistor 203 is on in the period C, andoff in the periods A, B, D, and E. Thus, in the period C, the potentialof the line 113 is applied to the node 12, so that a voltage requiredfor the capacitor 201 to operate can be held with reliability.Alternatively, in the period C, the time required for the capacitor 201to hold a voltage can be made longer, so that the capacitance of thecapacitor 201 can be increased. If the capacitance of the capacitor 201is large, the potential of the node 12 in the period D can be increased.

In this embodiment, for example since the off-state current of thetransistor 202 is low, the amount of charge lost from the capacitor 201can be reduced. Thus, it is possible to suppress a reduction in the highpotential of the node 12 and an increase in the low potential of thenode 12. Therefore, it is possible to extend the time from the start ofthe period A to the start of the next period A. Thus, the drivefrequency can be lowered. As a result, the range of the drive frequencyat which the semiconductor device can operate can be widened.

Of the circuits of this embodiment, each of the following structures isone embodiment of the present invention: the semiconductor deviceincluding the transistor 101, the transistor 103, and the transistor 104(see FIG. 6A); the semiconductor device including the transistor 101,the transistor 102, and the transistor 104 (see FIG. 6B); thesemiconductor device including the transistor 101, the transistor 102,the transistor 103, and the transistor 104 (see FIGS. 6C and 6D); thesemiconductor device including the transistor 101, the transistor 102,the transistor 104, and the transistor 105 (see FIG. 6E); and thesemiconductor device including the transistor 101, the transistor 102,the transistor 103, the transistor 104, and the transistor 105 (see FIG.6F).

Embodiment 2

In this embodiment, a shift register circuit in a display device whichis one embodiment of the present invention will be described. A shiftregister circuit of this embodiment can include any of the circuits ofEmbodiment 1. Further, the shift register circuit of this embodiment canbe used as a driver circuit of a display device, such as a gate drivercircuit and/or a source driver circuit.

FIG. 8 shows an example of the configuration of a shift register circuitthat includes N pieces of circuits 301 (circuits 301_1 to 301_N). Any ofthe circuits described in Embodiment 1 can be used as the circuit 301.FIG. 8 shows an example of the case where the circuit shown in FIG. 1Ais used as the circuit 301.

Connections in the shift register circuit shown in FIG. 8 will bedescribed. Connections in a circuit 301_i (i is included in 2 to N−1)will be described as an example. The circuit 301_i is connected to aline 311_i, a line 311_i−1, a line 311_i+1, either a line 312 or a line313, and a line 314. Specifically, in the circuit 301_i, the line 112 isconnected to the line 311_i; the line 114 is connected to the line311_i−1; the line 115 is connected to the line 311_i+1; the line 111 isconnected to either the line 312 or the line 313; and the line 113 isconnected to the line 314. Note that in the case where the line 111 isconnected to the line 312 in the circuit 301_i, the line 111 isconnected to the line 313 in a circuit 301_i+1 and a circuit 301_i−1.The circuit 301_1 differs from the circuit 301_i in that the line 114 isconnected to a line 315. The circuit 301_N differs from the circuit301_i in that the line 115 is connected to an output terminal of a dummycircuit (not illustrated), a line to which a reset signal is inputted(not illustrated), or the line 315, or the like.

The operation of the shift register circuit shown in FIG. 8 will bedescribed with reference to a timing diagram of FIG. 9 .

An example of the operation of the circuit 301_i will be described.First, the potential of the line 311_i−1 (potential V311_i−1) becomesV1. Then, the circuit 301_i performs the operation of the period A, sothat the potential of the line 311_i (potential V311_i) becomes V2.After that, the potential of the line 312 (potential V312) and thepotential of the line 313 (potential V313) are inverted. Then, thecircuit 301_i performs the operation of the period B, so that thepotential of the line 311_i becomes V1. After that, the potential of theline 312 and the potential of the line 313 are inverted, so that thepotential of the line 311_i+1 (potential V311_i+1) becomes V1. Then, thecircuit 301_i performs the operation of the period C, so that thepotential of the line 311_i becomes V2. After that, the circuit 301_irepeats the operation of the period D and the operation of the period Ein order until the potential of the line 311_i−1 becomes V1 again, sothat the potential of the line 311_i remains to be V2. Note that thecircuit 301_1 differs from the circuit 301_i in that it performs theoperation of the period A when the potential of the line 315 (potentialV315) becomes V1.

As described above, the potentials of the lines 311_1 to 311_N(potentials V311_1 to V311_N) can become V1 in order.

An output signal of the shift register circuit is inputted to the line311. A clock signal is inputted to the line 312. A clock signal that isout of phase with the clock signal inputted to the line 312 or a signalobtained by inverting the clock signal inputted to the line 312 isinputted to the line 313. The voltage V2 is applied to the line 314. Astart signal is inputted to the line 315.

The line 311 is used for transmitting an output signal of the shiftregister circuit to a circuit such as a pixel circuit or ademultiplexer. The line 311 functions as a signal line or a gate line.Each of the line 312 and the line 313 is used for transmitting a signalsuch as a clock signal from an external circuit such as a controller tothe shift register circuit of this embodiment. Each of the line 312 andthe line 313 functions as a signal line or a clock line. The line 314 isused for supplying power supply voltage such as the voltage V2 from anexternal circuit such as a power supply circuit to the shift registercircuit of this embodiment. The line 314 functions as a power supplyline, a negative supply line, or a ground line. The line 315 is used fortransmitting a start signal from an external circuit such as acontroller to the shift register circuit of this embodiment. The line315 functions as a signal line.

The shift register circuit shown in FIG. 8 can have a function ofswitching the scanning direction when the shift register includestransistors. That is, the shift register circuit can switch a drivingmethod in which the potentials of the lines 311_1 to 311_N become V1 inorder and a driving method in which the potentials of the lines 311_N to311_1 become V1 in order. FIG. 10 shows an example of the shift registercircuit including switches for changing the scanning direction. FIG. 10shows circuits 301_i−1 to 301_i+1 as an example. The shift registercircuit shown in FIG. 10 includes N number of circuits 301, N number oftransistors 302 (transistors 302_1 to 302_N), N number of transistors303 (transistors 303_1 to 303_N), N transistors 304 (transistors 304_1to 304_N), and N transistors 305 (transistors 305_1 to 305_N). Forexample, a first terminal of the transistor 302_i is connected to a line311_i−1; a second terminal of the transistor 302_i is connected to theline 114 of the circuit 301_i; and a gate of the transistor 302_i isconnected to the line 315. A first terminal of the transistor 303_i isconnected to the line 311_i−1; a second terminal of the transistor 303_iis connected to the line 115 of the circuit 301_i; and a gate of thetransistor 303_i is connected to the line 316. A first terminal of thetransistor 304_i is connected to a line 311_i+1; a second terminal ofthe transistor 304_i is connected to the line 114 of the circuit 301_i;and a gate of the transistor 304_i is connected to the line 316. A firstterminal of the transistor 305_i is connected to the line 311_i+1; asecond terminal of the transistor 305_i is connected to the line 115 ofthe circuit 301_i; and a gate of the transistor 305_i is connected tothe line 315.

An example of the operation of the shift register circuit shown in FIG.10 will be described. In the driving method in which the potentials ofthe lines 311_1 to 311_N become V1 in order, an H-level signal ispreferably inputted to the line 315, and an L-level signal is preferablyinputted to the line 316. Consequently, the transistor 302_i is turnedon, the transistor 303_i is turned off, the transistor 304_i is turnedoff, and the transistor 305_i is turned on. Thus, a signal outputtedfrom the line 311_i is inputted to the line 114 of the circuit 301_i+1and the line 115 of the circuit 301_i−1. In the driving method in whichthe potentials of the lines 311_N to 311_1 become V1 in order, line 315an L-level signal is preferably inputted to the line 315, and an H-levelsignal is preferably inputted to the line 316. Consequently, thetransistor 302_i is turned off, the transistor 303_i is turned on, thetransistor 304_i is turned on, and the transistor 305_i is turned off.Thus, a signal outputted from the line 311_i is inputted to the line 115of the circuit 301_i+1 and the line 114 of the circuit 301_i−1.

Note that the amplitude voltage of a signal inputted to one or both ofthe line 315 and the line 316 is preferably higher than that of a signalinputted to at least one of the N number of lines 311, the line 312, andthe line 313.

Embodiment 3

In this embodiment, an example of a transistor included in the circuitof Embodiment 1 or 2 will be described. Specifically, examples of thestructure of a transistor whose channel region is formed using an oxidesemiconductor and fabrication steps thereof will be described.

As the oxide semiconductor, the following oxides can be used: anIn—Sn—Ga—Zn—O-based oxide semiconductor that is an oxide of four metalelements; an In—Ga—Zn—O-based oxide semiconductor, an In—Sn—Zn—O-basedoxide semiconductor, an In—Al—Zn—O-based oxide semiconductor, aSn—Ga—Zn—O-based oxide semiconductor, an Al—Ga—Zn—O-based oxidesemiconductor, or a Sn—Al—Zn—O-based oxide semiconductor that is anoxide of three metal elements; an In—Zn—O-based oxide semiconductor, aSn—Zn—O-based oxide semiconductor, an Al—Zn—O-based oxide semiconductor,a Zn—Mg—O-based oxide semiconductor, a Sn—Mg—O-based oxidesemiconductor, or an In—Mg—O-based oxide semiconductor that is an oxideof two metal elements; an In—O-based oxide semiconductor; a Sn—O-basedoxide semiconductor; a Zn—O-based oxide semiconductor; and the like.Further, SiO₂ may be contained in the oxide semiconductor.

For the oxide semiconductor, a substance represented by InMO₃(ZnO)_(m)(m>0, where m is not a natural number) can be used. Here, M denotes oneor more metal elements selected from Ga, Al, Mn, or Co. For example, Mcan be Ga, Ga and Al, Ga and Mn, Ga and Co, or the like. Among oxidesemiconductor semiconductors whose composition formulae are expressed byInMO₃(ZnO)_(m) (m>0, where m is not a natural number), an oxidesemiconductor which includes Ga as M is referred to as theIn—Ga—Zn—O-based oxide semiconductor, and a thin film of theIn—Ga—Zn—O-based oxide semiconductor is also referred to as anIn—Ga—Zn—O-based film. In addition, an oxide semiconductor materialexpressed by In—Ga—Zn—O in this specification is InGaO₃(ZnO)_(m) (m>0,where m is not a natural number), and it can be confirmed by analysisusing ICP-MS or RBS that m is not a natural number.

An example of a method for fabricating a transistor whose channel regionis formed using an oxide semiconductor will be described with referenceto FIGS. 11A to 11D.

FIGS. 11A to 11D illustrate an example of the cross-sectional structureof a transistor. A transistor 410 shown in FIGS. 11A to 11D is abottom-gate channel-etched transistor.

Although a single-gate transistor is shown in FIGS. 11A to 11D, amulti-gate transistor including a plurality of channel regions can beformed when needed.

Steps of forming the transistor 410 over a substrate 400 will bedescribed below with reference to FIGS. 11A to 11D.

First, a conductive film is formed over the substrate 400 having aninsulating surface. Then, a gate electrode layer 411 is formed through afirst photolithography process.

Although there is no particular limitation on a substrate which can beused as the substrate 400 having an insulating surface, it is necessarythat the substrate have at least heat resistance high enough towithstand heat treatment to be performed later. For example, a glasssubstrate including barium borosilicate glass, aluminoborosilicateglass, or the like can be used. In the case where the temperature of theheat treatment to be performed later is high, a glass substrate whosestrain point is 730° C. or higher is preferably used.

An insulating film serving as a base film may be provided between thesubstrate 400 and the gate electrode layer 411. The base film has afunction of preventing diffusion of an impurity element from thesubstrate 400, and can be formed to have a single-layer structure or alayered structure including one or more films selected from a siliconnitride film, a silicon oxide film, a silicon nitride oxide film, or asilicon oxynitride film.

The gate electrode layer 411 can be formed to have a single-layerstructure or a layered structure including a metal material such asmolybdenum, titanium, chromium, tantalum, tungsten, aluminum, copper,neodymium, or scandium; or an alloy material which contains the metalmaterial as its main component.

Then, a gate insulating layer 402 is formed over the gate electrodelayer 411.

The gate insulating layer 402 can be formed to have a single-layerstructure or a layered structure including a silicon oxide layer, asilicon nitride layer, a silicon oxynitride layer, a silicon nitrideoxide layer, or an aluminum oxide layer by plasma-enhanced CVD,sputtering, or the like. Alternatively, a high-k material such ashafnium oxide (HfO_(x)) or tantalum oxide (TaO_(x)) can be used for thegate insulating layer. The thickness of the gate insulating layer 402 is100 to 500 nm. In the case where the gate insulating layer 402 is formedto have a layered structure, a first gate insulating layer having athickness of 50 to 200 nm and a second gate insulating layer having athickness of 5 to 300 nm are stacked.

In this embodiment, as the gate insulating layer 402, a siliconoxynitride layer is formed to a thickness of 100 nm or less byplasma-enhanced CVD.

Further, as the gate insulating layer 402, a silicon oxynitride film maybe formed using a high-density plasma apparatus. Here, a high-densityplasma apparatus refers to an apparatus which can realize a plasmadensity of 1×10¹¹/cm³ or higher. For example, plasma is generated byapplication of a microwave power of 3 to 6 kW so that an insulating filmis formed. Since the insulating film formed using the high-densityplasma apparatus can have a uniform thickness, the insulating film hasexcellent step coverage. Further, as for the insulating film formedusing the high-density plasma apparatus, the thickness of a thin filmcan be controlled precisely.

The insulating film formed using the high-density plasma apparatus isgreatly different from an insulating film formed using a conventionalparallel plate PCVD apparatus. The etching rate of the insulating filmformed using the high-density plasma apparatus is lower than that of theinsulating film formed using the conventional parallel plate PCVDapparatus by 10% or more or 20% or more in the case where the etchingrates with the same etchant are compared to each other. Thus, it can besaid that the insulating film formed using the high-density plasmaapparatus is a dense film.

An oxide semiconductor (a highly purified oxide semiconductor) which ismade to be intrinsic (i-type) or substantially intrinsic in a later stepis highly sensitive to an interface state and interface charge; thus, aninterface between the oxide semiconductor and the gate insulating layeris important. Thus, the gate insulating layer (GI) which is in contactwith the highly purified oxide semiconductor needs high quality.Therefore, high-density plasma-enhanced CVD using microwaves (2.45 GHz)is preferable because a dense high-quality insulating film having a highwithstand voltage can be formed. This is because when the highlypurified oxide semiconductor is in close contact with the high-qualitygate insulating layer, the interface state can be reduced and interfaceproperties can be favorable. It is important that the gate insulatinglayer have lower interface state density with an oxide semiconductor anda favorable interface as well as having favorable film quality as a gateinsulating layer.

Then, an oxide semiconductor film 430 is formed to a thickness of 2 to200 nm over the gate insulating layer 402. As the oxide semiconductorfilm 430, an In—Ga—Zn—O-based oxide semiconductor film, an In—Zn—O-basedoxide semiconductor film, or the like is used. In this embodiment, theoxide semiconductor film 430 is deposited by sputtering with the use ofan In—Ga—Zn—O-based oxide semiconductor target. A cross-sectional viewat this stage corresponds to FIG. 11A. Alternatively, the oxidesemiconductor film 430 can be deposited by sputtering in a rare gas(typically argon) atmosphere, an oxygen atmosphere, or an atmosphereincluding a rare gas (typically argon) and oxygen.

Here, deposition is performed using a metal oxide target containing In,Ga, and Zn (In₂O₃:Ga₂O₃:ZnO=1:1:1 [molar ratio]). The depositioncondition is set as follows: the distance between the substrate and thetarget is 100 mm; the pressure is 0.2 Pa; the direct current (DC) poweris 0.5 kW; and the atmosphere is an atmosphere containing argon andoxygen (argon:oxygen=30 sccm:20 sccm and the flow rate ratio of oxygenis 40%). Note that it is preferable that pulsed direct-current (DC)power be used because powdery substances generated in deposition can bereduced and the film thickness can be uniform. The thickness of anIn—Ga—Zn—O-based film is 5 to 200 nm. In this embodiment, as the oxidesemiconductor film, a 20-nm-thick In—Ga—Zn—O-based film is deposited bysputtering with the use of an In—Ga—Zn—O-based metal oxide target. Next,the oxide semiconductor film 430 is processed into an island-shapedoxide semiconductor layer through a second photolithography process.

Then, the oxide semiconductor layer is dehydrated or dehydrogenated. Thetemperature of first heat treatment for dehydration or dehydrogenationis 400 to 750° C., preferably higher than or equal to 400° C. and lowerthan the strain point of the substrate. Here, after the substrate is putin an electric furnace which is a kind of heat treatment apparatus andheat treatment is performed on the oxide semiconductor layer at 450° C.for one hour in a nitrogen atmosphere, water and hydrogen are preventedfrom being mixed into the oxide semiconductor layer again by preventingthe substrate from being exposed to the air; thus, oxide semiconductorlayer 431 is obtained (see FIG. 11B).

Note that the heat treatment apparatus is not limited to an electricfurnace, and may be provided with a device for heating an object to beprocessed by thermal conduction or thermal radiation from a heater suchas a resistance heater. For example, an RTA (rapid thermal annealing)apparatus such as a GRTA (gas rapid thermal annealing) apparatus or anLRTA (lamp rapid thermal annealing) apparatus can be used. An LRTAapparatus is an apparatus for heating an object to be processed byradiation of light (an electromagnetic wave) emitted from a lamp such asa halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arclamp, a high pressure sodium lamp, or a high pressure mercury lamp. AGRTA apparatus is an apparatus with which heat treatment is performedusing a high-temperature gas. As the gas, an inert gas which does notreact with an object to be processed by heat treatment, such as nitrogenor a rare gas such as argon, is used.

For example, as the first heat treatment, GRTA may be performed asfollows. The substrate is transferred and put in an inert gas heated ata high temperature of 650 to 700° C., is heated for several minutes, andis transferred and taken out of the inert gas heated at the hightemperature. GRTA enables short-time high-temperature heat treatment.

Note that in the atmosphere of the first heat treatment, it ispreferable that water, hydrogen, or the like be not contained innitrogen, a rare gas such as helium, neon, or argon, or dry air. Forexample, the purity of nitrogen or a rare gas such as helium, neon, orargon which is introduced into the heat treatment apparatus ispreferably 6N (99.9999%) or higher, more preferably 7N (99.99999%) orhigher (that is, the impurity concentration is 1 ppm or lower,preferably 0.1 ppm or lower).

In addition, the first heat treatment for the oxide semiconductor layercan be performed on the oxide semiconductor film 430 before beingprocessed into the island-shaped oxide semiconductor layer. In thatcase, the substrate is taken out of the heat apparatus after the firstheat treatment, and then the second photolithography process isperformed.

Further, in the case where an opening portion is formed in the gateinsulating layer 402, the formation of the opening portion may beperformed before or after the oxide semiconductor film 430 is dehydratedor dehydrogenated.

Note that the etching of the oxide semiconductor film 430 here is notlimited to wet etching, and may be dry etching.

As an etching gas used for dry etching of the oxide semiconductor film430, a gas containing chlorine (e.g., chlorine (Cl₂) or borontrichloride (BCl₃)) is preferably used.

As an etchant used for wet etching of the oxide semiconductor film 430,a solution obtained by mixture of phosphoric acid, acetic acid, andnitric acid, an ammonia hydrogen peroxide mixture (a hydrogen peroxidesolution at 31 wt %: ammonia water at 28 wt %: water=5:2:2), or the likecan be used. Alternatively, ITO-07N (produced by KANTO CHEMICAL CO.,INC.) may be used.

Next, a metal conductive film is formed over the gate insulating layer402 and the oxide semiconductor layer 431. The metal conductive film maybe formed by sputtering or vacuum evaporation. As the material of themetal conductive film, an element selected from aluminum (Al), chromium(Cr), copper (Cu), tantalum (Ta), titanium (Ti), molybdenum (Mo),tungsten (W), neodymium (Nd), or scandium (Sc); an alloy including anyof the elements; an alloy including any of these elements incombination; or the like can be used. Alternatively, a nitride film ofany of the above-described elements may be used. Alternatively, one ormore materials selected from manganese (Mn), magnesium (Mg), zirconium(Zr), beryllium (Be), and yttrium (Y) may be used. Further, the metalconductive film may have a single-layer structure or a layered structureof two or more layers. For example, a single-layer structure of analuminum film containing silicon, a two-layer structure in which atitanium film is stacked over an aluminum film, a three-layer structurein which a titanium film, an aluminum film, and a titanium film arestacked in that order, and the like can be given.

When heat treatment is performed after the formation of the metalconductive film, it is preferable that the metal conductive film haveheat resistance high enough to withstand the heat treatment.

A resist mask is formed over the metal conductive film through a thirdphotolithography process; a source electrode layer 415 a and a drainelectrode layer 415 b are formed by selective etching; then, the resistmask is removed (see FIG. 11C).

In this embodiment, a titanium film is used as the metal conductivefilm, an In—Ga—Zn—O-based oxide is used for the oxide semiconductorlayer 431, and an ammonia hydrogen peroxide solution (a mixture ofammonia, water, and a hydrogen peroxide solution) is used as an etchant.

Note that in the third photolithography process, only part of the oxidesemiconductor layer 431 is etched so that an oxide semiconductor layerhaving a groove (a depression) is formed in some cases.

In order to reduce the number of photomasks used in the photolithographyprocesses and to reduce the number of processes, an etching process maybe performed using a multi-tone mask which is an exposure mask throughwhich light is transmitted to have a plurality of intensities. A resistmask formed using a multi-tone mask has a plurality of thicknesses andcan be changed in shape by ashing; therefore, the resist mask can beused in a plurality of etching processes for processing films intodifferent patterns. Therefore, a resist mask corresponding to at leasttwo or more kinds of different patterns can be formed by one multi-tonemask. Thus, the number of exposure masks and the number of correspondingphotolithography processes can be reduced, so that the process can besimplified.

Next, plasma treatment is performed using a gas such as nitrous oxide(N₂O), nitrogen (N₂), or argon (Ar). By this plasma treatment, absorbedwater and the like which attach to a surface of the oxide semiconductorlayer exposed are removed. Alternatively, plasma treatment may beperformed using a mixture gas of oxygen and argon.

After the plasma treatment, an oxide insulating layer 416 which servesas a protective insulating film and is in contact with part of the oxidesemiconductor layer 431 is formed without exposure to the air.

The oxide insulating layer 416 can be formed to have a thickness of atleast 1 nm or more by a method by which an impurity such as water orhydrogen is not mixed into the oxide insulating layer 416, such assputtering, as appropriate. When hydrogen is contained in the oxideinsulating layer 416, hydrogen enters the oxide semiconductor layer, soa backchannel of the oxide semiconductor layer 431 has lower resistance(has n-type conductivity) and a parasitic channel is formed. Therefore,it is important that a deposition method in which hydrogen is not usedbe employed in order that the oxide insulating layer 416 contain aslittle hydrogen as possible.

In this embodiment, a 200-nm-thick silicon oxide film is deposited asthe oxide insulating layer 416 by sputtering. The substrate temperatureat the time of deposition is in the range of room temperature to 300°C., and 100° C. in this embodiment. The silicon oxide film can bedeposited by sputtering in a rare gas (typically argon) atmosphere, anoxygen atmosphere, or an atmosphere including a rare gas (typicallyargon) and oxygen. Further, a silicon oxide target or a silicon targetcan be used as a target. For example, a silicon oxide film can bedeposited using a silicon target in an atmosphere including oxygen andnitrogen by sputtering.

Next, second heat treatment (preferably at 200 to 400° C., for example,250 to 350° C.) is performed in an inert gas atmosphere, a dry airatmosphere, or an oxygen gas atmosphere. For example, the second heattreatment is performed at 250° C. for one hour in a nitrogen atmosphere.Through the second heat treatment, part of the oxide semiconductor layer(a channel region) is heated while being in contact with the oxideinsulating layer 416. Thus, oxygen is supplied to the part of the oxidesemiconductor layer (the channel region).

Through the above steps, after the heat treatment for dehydration ordehydrogenation is performed on the oxide semiconductor layer, the partof the oxide semiconductor layer (the channel region) is selectivelymade to be in an oxygen excess state. These steps allow the transistor410 to be formed.

Further, heat treatment may be performed at 100 to 200° C. for 1 to 30hours in an air atmosphere. In this embodiment, the heat treatment isperformed at 150° C. for 10 hours. This heat treatment may be performedat a fixed heating temperature. Alternatively, the following change inthe heating temperature may be conducted more than once repeatedly. Thisheat treatment can be performed at a constant heating temperature orfollow repeated temperature cycles where the temperature rises from roomtemperature to a heating temperature of 100 to 200° C. and drops fromthe a heating temperature to room temperature.

A protective insulating layer may be formed over the oxide insulatinglayer 416. For example, a silicon nitride film is formed by RFsputtering. Since RF sputtering has high productivity, it is preferablyused as a deposition method of the protective insulating layer. Theprotective insulating layer is formed using an inorganic insulating filmwhich does not contain an impurity such as moisture, a hydrogen ion, andOH⁻ and blocks entry of such an impurity from the outside, typically asilicon nitride film, an aluminum nitride film, a silicon nitride oxidefilm, or an aluminum oxynitride film. In this embodiment, as theprotective insulating layer, a protective insulating layer 403 is formedusing a silicon nitride film (see FIG. 11D).

In this embodiment, the oxide semiconductor layer of the transistor 410is an intrinsic (i-type) or substantially intrinsic oxide semiconductorlayer obtained by removal of hydrogen, which is an n-type impurity, fromthe oxide semiconductor and the increase in purity so that an impurityother than the main components of the oxide semiconductor is included aslittle as possible. In other words, the oxide semiconductor layer of thetransistor 410 is a highly purified intrinsic (i-type) semiconductorlayer or a semiconductor layer which is close to a highly purifiedi-type semiconductor layer not by adding an impurity but by removing animpurity such as hydrogen or water as much as possible. In this manner,the Fermi level (E_(f)) can be equal to the intrinsic Fermi level(E_(i)).

It is said that the band gap (E_(g)) of the oxide semiconductor is 3.15eV and electron affinity (χ) is 4.3 eV. The work function of titanium(Ti) used for the source electrode layer and the drain electrode layeris substantially equal to the electron affinity (χ) of the oxidesemiconductor. In this case, the Schottky electron barrier is not formedat an interface between the metal and the oxide semiconductor.

For example, even in the case of a transistor whose channel width W is1×10⁴ μm and whose channel length L is 3 μm, off-state current at roomtemperature can be 10⁻¹³ A or less and a subthreshold swing can be 0.1V/decade (the thickness of the gate insulating layer is 100 nm).

By the increase in purity so that an impurity other than the maincomponents of the oxide semiconductor may be included as little aspossible in this manner, the transistor 410 can operate in a favorableway.

In order to prevent variation in electrical characteristics of the oxidesemiconductor, an impurity that causes the variation, such as hydrogen,moisture, a hydroxyl group, or hydride (also referred to as a hydrogencompound), is intentionally removed. Additionally, the oxidesemiconductor becomes a highly purified electrically i-type (intrinsic)oxide semiconductor by supply of oxygen which is a main component of theoxide semiconductor that is simultaneously reduced in a step of removingthe impurity.

Therefore, it is preferable that the amount of hydrogen in the oxidesemiconductor be as small as possible. Further, the number of carriersin the highly purified oxide semiconductor is significantly small (closeto zero), and the carrier density is lower than 1×10¹²/cm³, preferably1×10¹¹/cm³ or lower. That is, the carrier density of the oxidesemiconductor layer can be extremely close to zero. Since the number ofcarriers in the oxide semiconductor layer is significantly small, theoff-state current of the transistor can be reduced. It is preferablethat the off-state current be as low as possible. The amount of currentper micrometer of the channel width (W) in the transistor is 100 aA orless, preferably 10 zA (zepto-ampere) or less, more preferably 1 zA orless. Further, the transistor has no PN junction and does notdeteriorate due to hot carriers; thus, the electrical characteristics ofthe transistor are not adversely affected.

In a transistor whose channel region is formed using an oxidesemiconductor which is highly purified by drastic removal of hydrogencontained in an oxide semiconductor layer as described above, theoff-state current can be extremely low. In other words, in circuitdesign, the oxide semiconductor layer can be regarded as an insulatorwhen the transistor is off. In contrast, the oxide semiconductor layeris estimated to have better current supply capability than asemiconductor layer including amorphous silicon when the transistor ison.

A thin film transistor including low-temperature polysilicon is designedon the assumption that off-state current is about 10000 times that of atransistor including an oxide semiconductor. Therefore, in the casewhere the transistor including an oxide semiconductor is compared withthe thin film transistor including low-temperature polysilicon, thevoltage hold time of the transistor including an oxide semiconductor canbe extended about 10000 times when storage capacitances are equal orsubstantially equal to each other (about 0.1 pF). For example, whenmoving images are displayed at 60 fps, the hold time for one signalwriting can be approximately 160 seconds, which is 10000 times that ofthe thin film transistor including low-temperature polysilicon. In thismanner, still images can be displayed on a display area even by lessfrequent writing of image signals.

Embodiment 4

In this embodiment, an example of a display device which is oneembodiment of the present invention will be described.

FIG. 12A shows an example of a display device including the shiftregister circuit of Embodiment 2. The display device shown in FIG. 12Aincludes a timing controller 5360; a driver circuit 5361 including asource driver circuit 5362, a gate driver circuit 5363_1, and a gatedriver circuit 5363_2; and a pixel area 5364. A plurality of sourcelines 5371 which extend from the source driver circuit 5362 and aplurality of gate lines 5372 which extend from the gate driver circuits5363_1 and 5363_2 are provided in the pixel area 5364. Pixels 5367 areprovided in matrix in regions where the plurality of source lines 5371and the plurality of gate lines 5372 intersect with each other

Note that the display device can include a lighting device, a controlcircuit thereof, and the like. In that case, the pixel 5367 preferablyincludes a liquid crystal element.

Note that it is possible not to provide one of the gate driver circuit5363_1 and the gate driver circuit 5363_2.

The timing controller 5360 has a function of controlling the operationof the driver circuit 5361 by supplying a control signal to the drivercircuit 5361. For example, the timing controller 5360 supplies a controlsignal such as a start signal SSP, a clock signal SCK, an inverted clocksignal SCKB, a video signal DATA, or a latch signal LAT to the sourcedriver circuit 5362. Further, the timing controller 5360 supplies acontrol signal such as a start signal GSP, a clock signal GCK, or aninverted clock signal GCKB to the gate driver circuit 5363_1 and thegate driver circuit 5363_2.

The source driver circuit 5362 has a function of outputting videosignals to the plurality of source lines 5371. The source driver circuit5362 can be referred to as a driver circuit, a signal line drivercircuit, or the like. Video signals are inputted to the pixels 5367.Display elements included in the pixels 5367 produce a grayscale inaccordance with the video signals.

The gate driver circuit 5363_1 and the gate driver 5363_2 each have afunction of sequentially selecting the pixels 5367 in each row. Each ofthe gate driver circuit 5363_1 and the gate driver circuit 5363_2 can bereferred to as a driver circuit or a scan line driver circuit. Thetiming of selecting the pixels 5367 is controlled when the gate drivercircuit 5363_1 and the gate driver circuit 5363_2 output gate signals tothe gate lines 5372.

Note that in the display device shown in FIG. 12A, the gate drivercircuit 5363_1 and the gate driver circuit 5363_2 can be formed over thesame substrate as the pixel area 5364. FIG. 12B shows an example of thecase where the gate driver circuit 5363_1 and the gate driver circuit5363_2 are formed over the same substrate as the pixel area 5364 (asubstrate 5380). Note that the substrate 5380 and an external circuitare connected to each other through a terminal 5381.

Note that in the display device shown in FIG. 12A, a part of the sourcedriver circuit 5362 (e.g., a switch, a multiplexer, a shift registercircuit, a decoder circuit, an inverter circuit, a buffer circuit,and/or a level shifter circuit) can be formed over the same substrate asthe pixel area 5364. FIG. 12C shows an example of the case where thegate driver circuit 5363_1, the gate driver circuit 5363_2, a part ofthe source driver circuit 5362 (denoted by a reference numeral 5362 a)are formed over the same substrate as the pixel area 5364 (the substrate5380) and another part of the source driver circuit 5362 (denoted by areference numeral 5362 b) is formed over a substrate that is differentfrom the substrate 5380.

The shift register circuit of Embodiment 2 can be used as the drivercircuit of the display device or a part of the driver circuit. When thedriver circuit of the display device includes the transistor ofEmbodiment 3 in particular, the usage of the shift register circuit inEmbodiment 2 leads to improvement in the drive capability of the drivercircuit. Thus, the display device can be made large. Alternatively, theresolution of the display area can be improved. Alternatively, thelayout area of the driver circuit can be reduced, thereby reducing theframe size of the display device.

Embodiment 5

In this embodiment, examples of an electronic appliance will bedescribed.

FIGS. 13A to 13H and FIGS. 14A to 14D illustrate electronic appliances.These electronic appliances can each include a housing 5000, a displayarea 5001, a speaker 5003, an LED lamp 5004, operation keys 5005(including a power switch or an operation switch), a connection terminal5006, a sensor 5007 (a sensor having a function of measuring force,displacement, position, speed, acceleration, angular velocity,rotational frequency, distance, light, liquid, magnetism, temperature,chemical substance, sound, time, hardness, electric field, current,voltage, electric power, radiation, flow rate, humidity, gradient,oscillation, smell, or infrared ray), a microphone 5008, and the like.

FIG. 13A shows a mobile computer which can include a switch 5009, aninfrared port 5010, and the like in addition to the above objects. FIG.13B shows a portable image reproducing device provided with a memorymedium (e.g., a DVD reproducing device), which can include a seconddisplay area 5002, a memory medium read portion 5011, and the like inaddition to the above objects. FIG. 13C shows a goggle-type displaywhich can include the second display area 5002, a support 5012, anearphone 5013, and the like in addition to the above objects. FIG. 13Dshows a portable game console which can include the memory medium readportion 5011 and the like in addition to the above objects. FIG. 13Eshows a projector which can include a light source 5033, a projectorlens 5034, and the like in addition to the above objects. FIG. 13F showsa portable game console which can include the second display area 5002,the memory medium read portion 5011, and the like in addition to theabove objects. FIG. 13G shows a television receiver which can include atuner, an image processing portion, and the like in addition to theabove objects. FIG. 13H shows a portable television receiver which caninclude a charger 5017 capable of transmitting and receiving signals andthe like in addition to the above objects. FIG. 14A shows a displaywhich can include a support 5018 and the like in addition to the aboveobjects. FIG. 14B shows a camera which can include an externalconnection port 5019, a shutter button 5015, an image reception portion5016, and the like in addition to the above objects. FIG. 14C shows acomputer which can include a pointing device 5020, the externalconnection port 5019, a reader/writer 5021, and the like in addition tothe above objects. FIG. 14D shows a mobile phone which can include anantenna, a tuner of one-segment (1seg digital TV broadcasts) partialreception service for mobile phones and mobile terminals, and the likein addition to the above objects.

The electronic appliances shown in FIGS. 13A to 13H and FIGS. 14A to 14Dcan have a variety of functions, for example, a function of displaying alot of information (e.g., a still image, a moving image, and a textimage) on a display area; a touch panel function; a function ofdisplaying a calendar, date, time, and the like; a function ofcontrolling processing with a lot of software (programs); a wirelesscommunication function; a function of being connected to a variety ofcomputer networks with a wireless communication function; a function oftransmitting and receiving a lot of data with a wireless communicationfunction; a function of reading a program or data stored in a memorymedium and displaying the program or data on a display area. Further,the electronic appliance including a plurality of display areas can havea function of displaying image information mainly on one display areawhile displaying text information on another display area, a function ofdisplaying a three-dimensional image by displaying images where parallaxis considered on a plurality of display areas, or the like. Furthermore,the electronic appliance including an image receiving portion can have afunction of photographing a still image, a function of photographing amoving image, a function of automatically or manually correcting aphotographed image, a function of storing a photographed image in amemory medium (an external memory medium or a memory medium incorporatedin the camera), a function of displaying a photographed image on thedisplay area, or the like. Note that functions which can be provided forthe electronic appliances shown in FIGS. 13A to 13H and FIGS. 14A to 14Dare not limited to them, and the electronic appliances can have avariety of functions.

FIG. 14E shows an example in which a display device is incorporated in abuilding structure. FIG. 14E shows a housing 5022, a display area 5023,a remote control 5024 which is an operation portion, a speaker 5025, andthe like. The display device is incorporated in the building structurein the form of a wall-hanging display and can be provided withoutrequiring a large space.

FIG. 14F shows another example in which a display device is incorporatedin a building structure. A display panel 5026 is incorporated in aprefabricated bath unit 5027, so that a bather can watch TV or the likethrough the display panel 5026.

Note that although this embodiment describes the wall and theprefabricated bath unit as examples of the building structures, thisembodiment is not limited to them: the display devices can be providedin a variety of building structures.

Next, examples in which display devices are incorporated in movingobjects will be described.

FIG. 14G shows an example in which a display device is incorporated in acar. A display panel 5028 is incorporated in a car body 5029 of the carand can display information related to the operation of the car orinformation inputted from inside or outside of the car on demand. Notethat the display panel 5028 may have a navigation function.

FIG. 14H shows an example in which a display device is incorporated in apassenger airplane. FIG. 14H shows a usage pattern when a display panel5031 is provided to a ceiling 5030 above a seat of the passengerairplane. The display panel 5031 is incorporated in the ceiling 5030through a hinge 5032, and a passenger can watch TV or the like throughthe display panel 5031 by stretching of the hinge 5032. The displaypanel 5031 is allowed by the control of the passenger to displayinformation.

Note that although bodies of a car and an airplane are shown as examplesof a moving object of this embodiment, this embodiment is not limited tothem: the semiconductor devices can be provided to a variety of objectssuch as two-wheeled vehicles, four-wheeled vehicles (including cars,buses, and the like), trains (including monorails, railroads, and thelike), and vessels.

The shift register circuit of Embodiment 2 is preferably incorporated inthe electronic appliance of this embodiment. The shift register circuitof Embodiment 2 in particular is preferably incorporated as a circuitfor driving the display area of the electronic appliance. When the shiftregister of Embodiment 2 is incorporated as a circuit for driving thedisplay area of the electronic appliance, the area of a driver circuitcan be reduced and the size of the display area can be increased.Further, the resolution of the display area can be improved.

This application is based on Japanese Patent Application serial No.2010-036902 filed with Japan Patent Office on Feb. 23, 2010, the entirecontents of which are hereby incorporated by reference.

1. (canceled)
 2. A semiconductor device comprising: a first transistor;a second transistor; a third transistor; a fourth transistor; a fifthtransistor; a sixth transistor; a seventh transistor; and an eighthtransistor, wherein the first transistor, the second transistor, thethird transistor, the fourth transistor, the fifth transistor, the sixthtransistor, the seventh transistor, and the eighth transistor have thesame conductivity type, wherein one of a source and a drain of the firsttransistor is electrically connected to a first line and the other ofthe source and the drain of the first transistor is electricallyconnected to a second line, wherein one of a source and a drain of thesecond transistor is electrically connected to the second line and theother of the source and the drain of the second transistor iselectrically connected to one of a source and a drain of the eighthtransistor, wherein one of a source and a drain of the third transistoris electrically connected to a gate of the first transistor, the otherof the source and the drain of the third transistor is electricallyconnected to the third line, and a gate of the third transistor iselectrically connected to a gate of the second transistor, wherein oneof a source and a drain of the fourth transistor is electricallyconnected to the gate of the first transistor, the other of the sourceand the drain of the fourth transistor is electrically connected to afourth line, and a gate of the fourth transistor is electricallyconnected to a fifth line, wherein one of a source and a drain of thefifth transistor is electrically connected to the gate of the firsttransistor, the other of the source and the drain of the fifthtransistor is electrically connected to the third line, and a gate ofthe fifth transistor is electrically connected to a sixth line, whereinone of a source and a drain of the sixth transistor is electricallyconnected to the gate of the second transistor, the other of the sourceand the drain of the sixth transistor is electrically connected to thethird line, and a gate of the sixth transistor is electrically connectedto the gate of the first transistor, wherein one of a source and a drainof the seventh transistor is electrically connected to the first line,the other of the source and the drain of the seventh transistor iselectrically connected to a seventh line, and a gate of the seventhtransistor is electrically connected to the gate of the firsttransistor, wherein the other of the source and the drain of the eighthtransistor is electrically connected to the second line and a gate ofthe eighth transistor is electrically connected to the sixth line,wherein a ratio of the channel width to the channel length of the fifthtransistor is smaller than a ratio of the channel width to the channellength of the fourth transistor, wherein the second line serves as afirst gate signal line, wherein the fourth line serves as a second gatesignal line, and wherein the sixth line serves as a third gate signalline.
 3. A semiconductor device comprising: a first transistor; a secondtransistor; a third transistor; a fourth transistor; a fifth transistor;a sixth transistor; a seventh transistor; and an eighth transistor,wherein the first transistor, the second transistor, the thirdtransistor, the fourth transistor, the fifth transistor, the sixthtransistor, the seventh transistor, and the eighth transistor have thesame conductivity type, wherein one of a source and a drain of the firsttransistor is electrically connected to a first line and the other ofthe source and the drain of the first transistor is electricallyconnected to a second line, wherein one of a source and a drain of thesecond transistor is electrically connected to the second line and theother of the source and the drain of the second transistor iselectrically connected to one of a source and a drain of the eighthtransistor, wherein one of a source and a drain of the third transistoris electrically connected to a gate of the first transistor, the otherof the source and the drain of the third transistor is electricallyconnected to the third line, and a gate of the third transistor iselectrically connected to a gate of the second transistor, wherein oneof a source and a drain of the fourth transistor is electricallyconnected to the gate of the first transistor, the other of the sourceand the drain of the fourth transistor is electrically connected to afourth line, and a gate of the fourth transistor is electricallyconnected to a fifth line, wherein one of a source and a drain of thefifth transistor is electrically connected to the gate of the firsttransistor, the other of the source and the drain of the fifthtransistor is electrically connected to the third line, and a gate ofthe fifth transistor is electrically connected to a sixth line, whereinone of a source and a drain of the sixth transistor is electricallyconnected to the gate of the second transistor, the other of the sourceand the drain of the sixth transistor is electrically connected to thethird line, and a gate of the sixth transistor is electrically connectedto the gate of the first transistor, wherein one of a source and a drainof the seventh transistor is electrically connected to the first line,the other of the source and the drain of the seventh transistor iselectrically connected to a seventh line, and a gate of the seventhtransistor is electrically connected to the gate of the firsttransistor, wherein the other of the source and the drain of the eighthtransistor is electrically connected to the second line and a gate ofthe eighth transistor is electrically connected to the sixth line,wherein a ratio of the channel width to the channel length of the fifthtransistor is smaller than a ratio of the channel width to the channellength of the fourth transistor, wherein the second line serves as afirst gate signal line, wherein the fourth line serves as a second gatesignal line, wherein the sixth line serves as a third gate signal line,and wherein the other of the source and the drain of the secondtransistor and the one of the source and the drain of the eighthtransistor are configured to be supplied with power supply voltage.
 4. Asemiconductor device comprising: a first transistor; a secondtransistor; a third transistor; a fourth transistor; a fifth transistor;a sixth transistor; a seventh transistor; and an eighth transistor,wherein the first transistor, the second transistor, the thirdtransistor, the fourth transistor, the fifth transistor, the sixthtransistor, the seventh transistor, and the eighth transistor have thesame conductivity type, wherein one of a source and a drain of the firsttransistor is electrically connected to a first line and the other ofthe source and the drain of the first transistor is electricallyconnected to a second line, wherein one of a source and a drain of thesecond transistor is electrically connected to the second line and theother of the source and the drain of the second transistor iselectrically connected to one of a source and a drain of the eighthtransistor, wherein one of a source and a drain of the third transistoris electrically connected to a gate of the first transistor, the otherof the source and the drain of the third transistor is electricallyconnected to the third line, and a gate of the third transistor iselectrically connected to a gate of the second transistor, wherein oneof a source and a drain of the fourth transistor is electricallyconnected to the gate of the first transistor, the other of the sourceand the drain of the fourth transistor is electrically connected to afourth line, and a gate of the fourth transistor is electricallyconnected to a fifth line, wherein one of a source and a drain of thefifth transistor is electrically connected to the gate of the firsttransistor, the other of the source and the drain of the fifthtransistor is electrically connected to the third line, and a gate ofthe fifth transistor is electrically connected to a sixth line, whereinone of a source and a drain of the sixth transistor is electricallyconnected to the gate of the second transistor, the other of the sourceand the drain of the sixth transistor is electrically connected to thethird line, and a gate of the sixth transistor is electrically connectedto the gate of the first transistor, wherein one of a source and a drainof the seventh transistor is electrically connected to the first line,the other of the source and the drain of the seventh transistor iselectrically connected to a seventh line, and a gate of the seventhtransistor is electrically connected to the gate of the firsttransistor, wherein the other of the source and the drain of the eighthtransistor is electrically connected to the second line and a gate ofthe eighth transistor is electrically connected to the sixth line,wherein a ratio of the channel width to the channel length of the fifthtransistor is smaller than a ratio of the channel width to the channellength of the fourth transistor, wherein the first line serves as aclock signal line, wherein the second line serves as a first gate signalline, wherein the fourth line serves as a second gate signal line,wherein the sixth line serves as a third gate signal line, and whereinthe other of the source and the drain of the second transistor and theone of the source and the drain of the eighth transistor are configuredto be supplied with power supply voltage.